This specification relates to polishing pads useful for polishing and planarizing substrates, such as semiconductor substrates or magnetic disks.
Polymeric polishing pads, such as polyurethane, polyamide, polybutadiene and polyolefin polishing pads represent commercially available materials for substrate planarization in the rapidly evolving electronics industry. Electronics industry substrates requiring planarization include silicon wafers, patterned wafers, flat panel displays and magnetic storage disks. In addition to planarization, it is essential that the polishing pad not introduce excessive numbers of defects, such as scratches or other wafer non-uniformities. Furthermore, the continued advancement of the electronics industry is placing greater demands on the planarization and defectivity capabilities of polishing pads.
For example, the production of semiconductors typically involves several chemical mechanical planarization (CMP) processes. In each CMP process, a polishing pad in combination with a polishing solution, such as an abrasive-containing polishing slurry or an abrasive-free reactive liquid, removes excess material in a manner that planarizes or maintains flatness for receipt of a subsequent layer. The stacking of these layers combines in a manner that forms an integrated circuit. The fabrication of these semiconductor devices continues to become more complex due to requirements for devices with higher operating speeds, lower leakage currents and reduced power consumption. In terms of device architecture, this translates to finer feature geometries and increased numbers of metallization levels. These increasingly stringent device design requirements are driving the adoption of smaller and smaller line spacing with a corresponding increase in pattern density. The devices' smaller scale and increased complexity have led to greater demands on CMP consumables, such as polishing pads and polishing solutions. In addition, as integrated circuits' feature sizes decrease, CMP-induced defectivity, such as, scratching becomes a greater issue. Furthermore, integrated circuits' decreasing film thickness requires improvements in defectivity while simultaneously providing acceptable topography to a wafer substrate; these topography requirements demand increasingly stringent planarity, line dishing and small feature array erosion polishing specifications.
Historically, cast polyurethane polishing pads have provided the mechanical integrity and chemical resistance for most polishing operations used to fabricate integrated circuits. For example, polyurethane polishing pads have sufficient tensile strength for resisting tearing; abrasion resistance for avoiding wear problems during polishing; and stability for resisting attack by strong acidic and strong caustic polishing solutions. Unfortunately, the hard cast polyurethane polishing pads that tend to improve planarization, also tend to increase defects.
James et al., in US Pat. Pub. No. 2005/0079806, disclose a family of hard polyurethane polishing pads with planarization ability similar to IC1000™ polyurethane polishing pads, but with improved defectivity performance—IC1000 is a trademark of Rohm and Haas Company or its affiliates. Unfortunately, the polishing performance achieved with the polishing pad of James et al. varies with the polishing substrate and polishing conditions. For example, these polishing pads have limited advantage for polishing silicon oxide/silicon nitride applications, such as direct shallow trench isolation (STI) polishing applications. For purposes of this specification, silicon oxide refers to silicon oxide, silicon oxide compounds and doped silicon oxide formulations useful for forming dielectrics in semiconductor devices; and silicon nitride refers to silicon nitrides, silicon nitride compounds and doped silicon nitride formulations useful for semiconductor applications. These silicon compounds useful for creating semiconductor devices continue to evolve in different directions. Specific types of dielectric oxides in use include the following: TEOS formed from the decomposition of tetraethyloxysilicates, HDP (“high-density plasma”) and SACVD (“sub-atmospheric chemical vapor deposition”). There is an ongoing need for additional polishing pads that have superior planarization ability in combination with improved defectivity performance. In particular, there is a desire for polishing pads suitable for polishing oxide/SiN with an improved combination of planarization and defectivity polishing performance.